V. Yamuna , P. Meenakshi Vidya , S. Sudha. Design of Power Efficient Double Edge Triggered DLL Clock Generator. ijetst [Internet]. 2017Jun.30 [cited 2024Jul.1];4(06):5257-60. Available from: https://igmpublication.org/ijetst.in/index.php/ijetst/article/view/1135