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Abstract
The recent time witnesses a tremendous need for high performance digital signal Processing (DSP) systems for high end emerging applications like HD-TV, medical imaging, satellite communication, 3G mobile technologies etc. For all these applications, the sources of data are video signals. For transmission of video signals significant amount of bandwidth required. Since the captured video data contain huge amount of redundant data, there is an opportunity for video data compression keeping the picture quality intact. DCT is a well known technique used in video or image compression. DCT algorithms are computation intensive and involve large number of multiplication and addition operations. Therefore, with the increase in number of length of the DCT,the number of multiplication and addition operations also increase leading to larger chip area and performance degradation. The primary aspect of the 2-D DCT computation is to compute the DCT coefficients, where a large number of mathematical computations are required. This work is implemented on Matlab and hardware level by using of Verilog hardware language. Many researchers provided different architectures targeting area or speed or throughput with non scalable approach for computation..
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How to Cite
Shandilya, S., & Singh, K. (2015). Fast and Approximate processing unit for 2D Discrete Cosine System. International Journal of Emerging Trends in Science and Technology, 2(06). Retrieved from https://igmpublication.org/ijetst.in/index.php/ijetst/article/view/714
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2. K. Lee, M. Kim, N. Dutt, and N. Venkatasubramanian. Error exploiting video encoder to extend energy/QoS tradeoffs for mobile embedded systems. In IFIP Working Conference on Distributed and Parallel Embedded Systems, Sep 2008
3. http://www.cdnconnect.com/image-optimization-compression-reducing-file-sizes
4. Strang, Gilbert. "The discrete cosine transform." SIAM review 41.1 (1999): 135-
147.
5. Chitprasert, B., and K. R. Rao. "Discrete cosine transform filtering." Acoustics, Speech, and Signal Processing, 1990. ICASSP-90., 1990 International Conference on.
IEEE, 1990.
6. Haweel, Tarek I. "A new square wave transform based on the DCT." Signal processing 81.11 (2001): 2309-2319.
7. Kaliannan, Bhuvanan, and Vijaya Sankara Rao Pasupureddi. "Implementation of a Charge Redistribution Based 2-D DCT Architecture for Wireless Capsule Endoscopy." VLSI Design and 2013 12th International Conference on Embedded Systems (VLSID), 2013 26th International Conference on. IEEE, 2013.
8. Park, Jongsun, Soonkeon Kwon, and Kaushik Roy. "Low power reconfigurable DCT design based on sharing multiplication." Acoustics, Speech, and Signal Processing (ICASSP), 2002 IEEE International Conference on. Vol. 3. IEEE, 2002.
9. Yuebing Jiang; Pattichis, M., "A dynamically reconfigurable DCT architecture for maximum image quality subject to dynamic power and bitrate constraints," Image Analysis and Interpretation (SSIAI), 2012 IEEE Southwest Symposium on , vol., no., pp.189,192, 22-24 April 2012
10. Yuebing Jiang; Pattichis, M., "Dynamically recon_gurable DCT architectures based on bitrate, power, and image quality considerations," Image Processing (ICIP), 2012 19th IEEE International Conference on ,Sept. 30 2012-Oct. 3 2012
11. Jongsun Park; Jung-Hwan Choi; Roy, K., "Dynamic Bit-Width Adaptation in DCT: An Approach to Trade O_ Image Quality and Computation Energy,"Very Large Scale Integration (VLSI) Systems, IEEE Transactions on , May 2010
12. Wei Zheng; Yanchang Liu, "Research in a fast DCT algorithm based on JPEG," Consumer Electronics, Communications and Networks (CECNet), 2011 International Conference on , 16-18 April 2011
13. Emre, Y.; Chakrabarti, C., "Data-path and memory error compensation technique for low power JPEG implementation," Acoustics, Speech and Signal Processing (ICASSP), 2011 IEEE International Conference on , 22-27 May 2011
14. Whatmough, P.N.; Das, S.; Bull, D.M.; Darwazeh, I., "Circuit-Level Timing Error Tolerance for Low-Power DSP Filters and Transforms," Very Large Scale Integration (VLSI) Systems, IEEE Transactions on , June 2013
15. Gupta, V.; Mohapatra, D.; Raghunathan, A.; Roy, K., "Low-Power Digital Signal Processing Using Approximate Adders," Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on , Jan. 2013
16. De Silva, A.M.; Bailey, D.G.; Punchihewa, A., "Exploring the implementation of JPEG compression on FPGA," Signal Processing and Communication Systems (ICSPCS), 2012 6th International Conference on , 12-14 Dec. 2012
17. Kitsos, Paris; Voros, Nikolaos S.; Dagiuklas, Tasos; Skodras, Athanassios N., "A high speed FPGA implementation of the 2D DCT for Ultra High Definition video coding," Digital Signal Processing (DSP), 2013 18th International Conference on , 1-3 July 2013
18. Emre, Y.; Chakrabarti, C., "Energy and Quality-Aware Multimedia Signal Processing," Multimedia, IEEE Transactions on , Nov. 2013
19. Karakonstantis,G.; Banerjee, N.; Roy K.,"Process-Variation Resilient and Voltage-Scalable DCT Architecture for Robust Low-Power Computing," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2010.
20. Zhou Wang; Bovik, A.C.; Sheikh, H.R.; Simoncelli, E.P., "Image quality assessment: from error visibility to structural similarity," Image Processing,IEEE Transactions on , vol.13, no.4, pp.600,612, April 2004 doi:10.1109/TIP.2003.819861
21. Lin Zhang; Zhang, D.; Xuanqin Mou, "RFSIM: A feature based image quality assessment metric using Riesz transforms," Image Processing (ICIP), 2010 17th IEEE International Conference on , vol., no., pp.321,324, 26-29 Sept.2010
22. Lin Zhang; Zhang, D.; Xuanqin Mou; Zhang, D., "FSIM: A Feature Similarity Index for Image Quality Assessment," Image Processing, IEEE Transactions on , vol.20, no.8, pp.2378,2386, Aug. 2011
23. Xue, W.; Zhang, L.; Mou, X.; Bovik, A., "Gradient Magnitude Similarity Deviation: A Highly E_cient Perceptual Image Quality Index," Image Processing, IEEE Transactions on , vol.PP, no.99, pp.1,1
24. http://www.mathworks.in/