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Abstract
In this paper, Reed Solomon (RS) Encoder and Decoder and their implementation in Spartan 6 Field Programmable Gate Array (FPGA) is analyzed. RS codes are non-binary cyclic error correcting block codes. Here parity symbols are generated at the encoder end using a generator polynomial and added to the very end of the message symbols. Then the locations and magnitudes of errors in the received polynomial are determined by the RS decoder. The main objective of this project is to optimize the area used on FPGA which in turn minimizes the size and ultimately the cost. The paper covers the RS encoding and decoding algorithm, simulations and the implementation details of the encoder and decoder architecture. Register transfer level (RTL) of RS encoder and decoder is designed, simulated and implemented using Xilinx in Spartan 6 FPGA kit.
Keywords: FPGA, Key Equation Solver (KES), Reed Solomon (RS) Decoder, Reed Solomon (RS) Encoder and VHDL.##plugins.themes.academic_pro.article.details##
How to Cite
Borkar, H. L., & Bhonge, P. V. (2015). Design and Implementation of High Performance Reed Solomon Encoder and Decoder. International Journal of Emerging Trends in Science and Technology, 2(05). Retrieved from https://igmpublication.org/ijetst.in/index.php/ijetst/article/view/691
References
[1] Abhinav Agarwal, Man Cheuk Ng, and Arvind, “A Comparative Evaluation of High-Level Hardware Synthesis Using Reed–Solomon Decoderâ€, IEEE Embedded Systems Letters, VOL. 2, No. 3, September 2010.
[2] G. C. Cardarilli, S. Pontarelli, M. Re, and A. Salsano, “Concurrent Error Detection in Reed–Solomon Encoders &Decodersâ€, IEEE Transactions on very large scale integration (VLSI) systems, VOL. 15, No. 7, July 2007
[3] Rajeev Kumar Patial and Priyanka Dayal, “FPGA Implementation of Reed-Solomon Encoder and Decoder for Wireless Network 802.16â€, Int. Journal of Computer Appl’s (0975–8887) Vol 68– No.16,April 13.
[4] G. C. Cardarilli, S. Pontarelli, M. Re, and A. Salsan, “Analysis of Errors and Erasures in Parity Sharing RS Codecsâ€, IEEE transactions on computer VOL. 56, No. 12, December 2007.
[5] Diplaxmi Chaudhari, Mayura Bhujade and Pranali Dhumal, “VHDL Design and FPGA Implementation of Reed Solomon Encoder and Decoder for RS (7, 3)â€, International Journal of Science, Engineering and Technology Research (IJSETR), Volume 3, Issue 3, March 2014 563.
[6] Aqib Al Azad and Md Imam Shahed, “A Compact and Fast FPGA Based Implementation of Encoding and Decoding Algorithm Using Reed Solomon Codesâ€, International Journal of Future Computer and Communication, Vol. 3, No. 1, Feb. 2014.
[7] Sandeep Kaur, “VHDL implementation of Reed Solomon Codesâ€, Thapar Institute of Engineering and Technology, Patiala, 2006.
[8] Hazem Abd Elall Ahmed Elsaid, “Design and Implementation of Reed Solomon Decoder using Decomposed Inversion less Berlekamp-Massey Algorithmâ€, Faculty of Engineering, Cairo University Giza, Egypt,2010.
[9] Harikishore Kakarla, Madhavi Latha and Habibulla Khan, “Optimal Self Correcting Fault Free Error Coding Technique in Memory Operationâ€, International Journal of Computer Science & Information Technol-ogy (IJCSIT), Vol.3, No.3,June 2011.
[10] Zi-Yi Lam, Wai-Leong Pang, Chee-Pun Ooi, Sew-Kin Wong and Kah-Yoong Chan, “VHDL Modelling of Reed Solomon Decoderâ€, Research Journal of Applied Sciences, Engineering and Technology 4(23): 5193-5200, 2012 ISSN: 2040-7467© Maxwell Scientific Organization, 2012.
[11] S. Reed and G. Solomon, “Polynomial Codes Over Certain Finite Fields", SIAM Journal of Applied Maths, vol.8, pp.300–304
[12] R. J. McEliece, “Finite Fields for Computer Scientists and Engineersâ€, Boston, MA: Kluwer Academic, 1987.
[13] S. B. Wicker, “Error Control Systems for Digital Communication and Storageâ€, Englewood Cliffs, N.J.:Prentice-Hall, 1994.
[14] M. Kaur and V. Sharma, “Study of Forward Error Correction using Reed—Solomon Codesâ€, International Journal of Electronics Engineering, vol. 2, pp. 331 – 333, 2010.
[15] M. Purser, “Introduction to Error Correcting Codesâ€, Artech House, Boston-London, 1995.
[16] K. Sam. Shanmugam, “Digital and Analog Communication Systemâ€, The University of Michigan, Wiley, 1979.
C. K. P. Clarke, â€Reed-Solomon Error Correctionâ€, BBC Research & Development, White Paper WHP 031
[2] G. C. Cardarilli, S. Pontarelli, M. Re, and A. Salsano, “Concurrent Error Detection in Reed–Solomon Encoders &Decodersâ€, IEEE Transactions on very large scale integration (VLSI) systems, VOL. 15, No. 7, July 2007
[3] Rajeev Kumar Patial and Priyanka Dayal, “FPGA Implementation of Reed-Solomon Encoder and Decoder for Wireless Network 802.16â€, Int. Journal of Computer Appl’s (0975–8887) Vol 68– No.16,April 13.
[4] G. C. Cardarilli, S. Pontarelli, M. Re, and A. Salsan, “Analysis of Errors and Erasures in Parity Sharing RS Codecsâ€, IEEE transactions on computer VOL. 56, No. 12, December 2007.
[5] Diplaxmi Chaudhari, Mayura Bhujade and Pranali Dhumal, “VHDL Design and FPGA Implementation of Reed Solomon Encoder and Decoder for RS (7, 3)â€, International Journal of Science, Engineering and Technology Research (IJSETR), Volume 3, Issue 3, March 2014 563.
[6] Aqib Al Azad and Md Imam Shahed, “A Compact and Fast FPGA Based Implementation of Encoding and Decoding Algorithm Using Reed Solomon Codesâ€, International Journal of Future Computer and Communication, Vol. 3, No. 1, Feb. 2014.
[7] Sandeep Kaur, “VHDL implementation of Reed Solomon Codesâ€, Thapar Institute of Engineering and Technology, Patiala, 2006.
[8] Hazem Abd Elall Ahmed Elsaid, “Design and Implementation of Reed Solomon Decoder using Decomposed Inversion less Berlekamp-Massey Algorithmâ€, Faculty of Engineering, Cairo University Giza, Egypt,2010.
[9] Harikishore Kakarla, Madhavi Latha and Habibulla Khan, “Optimal Self Correcting Fault Free Error Coding Technique in Memory Operationâ€, International Journal of Computer Science & Information Technol-ogy (IJCSIT), Vol.3, No.3,June 2011.
[10] Zi-Yi Lam, Wai-Leong Pang, Chee-Pun Ooi, Sew-Kin Wong and Kah-Yoong Chan, “VHDL Modelling of Reed Solomon Decoderâ€, Research Journal of Applied Sciences, Engineering and Technology 4(23): 5193-5200, 2012 ISSN: 2040-7467© Maxwell Scientific Organization, 2012.
[11] S. Reed and G. Solomon, “Polynomial Codes Over Certain Finite Fields", SIAM Journal of Applied Maths, vol.8, pp.300–304
[12] R. J. McEliece, “Finite Fields for Computer Scientists and Engineersâ€, Boston, MA: Kluwer Academic, 1987.
[13] S. B. Wicker, “Error Control Systems for Digital Communication and Storageâ€, Englewood Cliffs, N.J.:Prentice-Hall, 1994.
[14] M. Kaur and V. Sharma, “Study of Forward Error Correction using Reed—Solomon Codesâ€, International Journal of Electronics Engineering, vol. 2, pp. 331 – 333, 2010.
[15] M. Purser, “Introduction to Error Correcting Codesâ€, Artech House, Boston-London, 1995.
[16] K. Sam. Shanmugam, “Digital and Analog Communication Systemâ€, The University of Michigan, Wiley, 1979.
C. K. P. Clarke, â€Reed-Solomon Error Correctionâ€, BBC Research & Development, White Paper WHP 031