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Abstract

Reduced Instruction Set Computer (RISC) is become a design theory that has accepted in engineering applications. Optimizing the gate capacity and performance of FPGA kit. This devices provides complex logic systems to be performed and implemented on  a  single device. So the main aim of this project is to design, study and implement an 8-bit Reduced Instruction Set Computer processor using XILINX Spartan 3E tool. The elevate feature of Spartan-3E reduces the cost per logic cell designed. The prominent feature of the RISC processor is that this processor is very simple. RISC processor support load/store architecture (Von Neumann). The main components of processor include the Arithmetic Logic Unit, Control unit, Shifter, and Rotator

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Author Biography

Dr. S. L. Lahudkar, Amit M. Mankar, Sudesh D. Bhong, JSPM’s, Imperial College Of Engineering & Research, Savitribai Phule Pune University, Pune

Department of Electronics & Telecommunication
How to Cite
Sudesh D. Bhong, D. S. L. L. A. M. M. (2015). Risc Processor Using VHDL. International Journal of Emerging Trends in Science and Technology, 2(03). Retrieved from https://igmpublication.org/ijetst.in/index.php/ijetst/article/view/554

References

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