Energy Aware 32 Bit Arithmetic and Logical Unit for Error Tolerant Applications

In this era of high end devices, the power efficient architecture is taking responsibility so as to reduce the
cost for maintenance. This becomes the critical task for embedded based device, graphical based processor
and similar DSP processors which suffers with low power. The core of every embedded device and processor
which in turn uses ALU as the workhorse. As we know if workhorse require less power, speed and area so
based on that workhorse complete system will make justice with SPAA metrics (Speed, Power, Area and
Accuracy). This paper proposed an architecture of 32 bit General Purpose ALU .The critical power
dissipation can be avoided by the application of clock gating of the hardware required and improving
architectural approach for this in which we divide ALU is four sub block of 8-8 bit. These 32 bit ALU is
identify input bit and according to that it will perform operation. Proposed architecture is combination of
four 8 bit ALU which is accurate, semi accurate and approximate. Due to these logic we can save power
consumption. The synthesized architecture is implemented by Hardware descriptive language (Verilog).
Analysis is performing on FPGA (Field Programmable Gate Array) level.