Design and Implementation of High-Speed Low Power Multipliers Using Reversible Logic

Reversible logic is one of the promising research areas in low power applications such as quantum
computing, optical information processing, DNA computing and also thermodynamic technology,
Nanotechnology and low power CMOS design. In this paper, a novel Reversible logic gate has been proposed
and novel architecture for multiplier is constructed by using ANU gate and PERES gate. A Multiplier is one
of the key hardware blocks in most fast processing system which is not only a high delay block but also a
major source of power dissipation. Power dissipation for Reversible logic gates is very less because of its
reversibility property. The main purposes of designing reversible logic are to decrease quantum cost, depth of
the circuits and the number of garbage outputs. The primary characteristics like garbage outputs, Constant
inputs and number of gates got decreased. The logical calculations also got decreased